1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor device structures. More particularly, the present invention relates to a method for creating depressions in a semiconductor substrate or film using laser ablation processes and using such depressions for defining precise electrically conductive elements along selected pathways in a semiconductor device structure, as well as related methods of fabricating semiconductor device assemblies.
2. Background of the Related Art
Connection lines (e.g., lead and/or bond connections), traces, signals and other elongated conductive elements are utilized in semiconductor device structures to carry electronic signals and other forms of electron flow between one region of the semiconductor device structure and another region thereof and between regions within the semiconductor device structure and external contacts (e.g., solder balls, bond pads and the like) associated therewith. Conventional methods for forming such elongated conductive elements may utilize a damascene process wherein one or more depressions are etched in an exposed surface of a semiconductor substrate or film, backfilled with an electrically conductive material, and polished back or “planarized” to be even (i.e., substantially coplanar) with respect to the exposed surface of the substrate or film.
As used herein, the term “depression” includes troughs, channels, vias, holes and other depressions in or through a material layer formed upon a semiconductor substrate. For instance, depressions may be used to define electrically conductive pathways that carry electronic signals between one region of a semiconductor device structure and another region thereof, and between regions within the semiconductor device structure and external contacts associated therewith, as well as providing power, ground, and bias to integrated circuitry of the semiconductor device structure. Such electrically conductive pathways may include, without limitation, depressions used to define traces or lines for signal lines, power and ground lines, and the like.
FIGS. 1A-1E schematically depict a conventional damascene process sequence for creating elongated conductive elements in the form of traces 26 in an interlevel dielectric layer 14. It will be understood by those of ordinary skill in the art that, while the process depicted illustrates formation of a plurality of generic conductive traces 26, such traces may be typically utilized for signal lines, power lines and ground lines, etc.
Referring to FIG. 1A, a cross-sectional view of a first intermediate structure 10 in the fabrication of a semiconductor device structure 24 having a plurality of traces 26 in the interlevel dielectric layer 14 thereof is illustrated. The first intermediate structure 10 includes an interlevel dielectric layer 14, e.g., thermally grown silicon dioxide (SiO2), which resides on a semiconductor substrate 12, such as a silicon wafer. It will be understood by those of ordinary skill in the art that the figures presented in conjunction with this description are not meant to be actual cross-sectional views of any particular portion of an actual semiconductor device, but are merely representations employed to more clearly and fully depict the conventional process sequence than would otherwise be possible. Elements common between the figures may maintain the same numeric designation.
A photoresist layer 16, comprising a conventional photoresist material, is disposed atop the interlevel dielectric layer 14 and one or more trace precursors in the form of trace depressions 18 are patterned in the photoresist layer 16 using conventional photolithography techniques comprising selective masking, exposure and development. The patterned trace depressions 18 may be of any shape or configuration including, but not limited to, circles, ovals, rectangles, elongated slots and the like.
As shown in FIG. 1B, the interlevel dielectric layer 14 is subsequently etched using the photoresist layer 16 as a mask so that the patterned trace depressions 18 are extended into the interlevel dielectric layer 14. Such etching processes are known to those of ordinary skill in the art and may include, without limitation, reactive ion etching (RIE) or an oxide etch. As shown in FIG. 1C, the photoresist layer 16 is subsequently removed by a conventional process, such as a wet-strip process, a tape lift-off technique, or combinations thereof, creating a second intermediate structure 20.
As shown in FIG. 1D, an electrically conductive material 22, (e.g., tungsten) is subsequently blanket deposited over the interlevel dielectric layer 14 such that the trace depressions 18 are filled therewith. The electrically conductive material 22 is then planarized using, e.g., a mechanical abrasion technique, such as chemical mechanical planarization (CMP), to isolate the electrically conductive material 22 in the trace depressions 18, as illustrated in FIG. 1E. Thus, a semiconductor device structure 24 including a plurality of traces 26 in the interlevel dielectric layer 14 thereof is fabricated.
For forming more complex electrically conductive pathways, for instance, those in which both an elongated conductive element (e.g., a trace) and one or more discrete, vertically extending conductive structures (e.g., vias, contacts) are to be defined in a single interlevel dielectric layer, a dual damascene process may be utilized. FIGS. 2A-2I illustrate a conventional dual damascene process sequence. Referring to FIG. 2A, a cross-sectional view of a first intermediate structure 10′ in the fabrication of a semiconductor device structure 24′ (FIG. 2I) having a plurality of traces 26′ (FIG. 2I) and a plurality of conductor-filled vias 32 (FIG. 2I) in the interlevel dielectric layer 14′ thereof is illustrated. The first intermediate structure 10′ includes an interlevel dielectric layer 14′, e.g., thermally grown SiO2, which resides on a semiconductor substrate 12′, such as a silicon wafer. A mask layer 28 having a plurality of trace precursors in the form of trace depressions 18′ patterned therein, is disposed atop the interlevel dielectric layer 14′. The patterned trace depressions 18′ may be of any shape or configuration including, but not limited to, circles, ovals, rectangles, elongated slots and the like.
As shown in FIG. 2B, a photoresist layer 16′, formed from a conventional photoresist material, is subsequently deposited atop the mask layer 28 such that the patterned trace depressions 18′ are filled therewith. Next, as shown in FIG. 2C, conventional photolithography in the form of selective masking, exposure and development of photoresist layer 16′ is performed on the photoresist layer 16′ to form a patterned photoresist layer 16″ having a plurality of vias 30 patterned therein which align with the trace depressions 18′ of the mask layer 28.
Referring to FIG. 2D, the interlevel dielectric layer 14′ is subsequently etched (e.g., by way of RIE) through the patterned photoresist layer 16″. The pattern of vias 30 is accordingly extended into the upper portion of the interlevel dielectric layer 14′.
As shown in FIG. 2E, the patterned photoresist layer 16″ is subsequently removed, forming a second intermediate structure 20′. Thereafter, the interlevel dielectric layer 14′ is etched using the mask layer 28 with the patterned trace depressions 18′ therein and the upper portion of the interlevel dielectric layer 14′ with the vias 30 therein as a mask. The result is shown in FIG. 2F, wherein the desired trace pattern is extended into the upper portion of the interlevel dielectric layer 14′ and the vias 30 in the upper portion of the interlevel dielectric layer 14′ are concurrently extended into the lower portion of the interlevel dielectric layer 14′.
Subsequently, as shown in FIG. 2G, the mask layer 28 is removed by a conventional process to create a third intermediate structure 34. An electrically conductive material 22′, e.g., tungsten, is then blanket deposited over the interlevel dielectric layer 14′ such that the trace depressions 18′ and vias 30 are filled therewith, as shown in FIG. 2H. The electrically conductive material 22′ is then planarized using, e.g., a mechanical abrasion technique such as chemical mechanical planarization (CMP), to isolate the electrically conductive material 22′ in the vias 30 and trace depressions 18′. The result of planarization is illustrated in FIG. 2I. Thus, a semiconductor device structure 24′ having a plurality of traces 26′ and a plurality of conductor-filled vias 32 defined in a single interlevel dielectric layer 14′ thereof is fabricated.
Further methods of forming damascene and dual damascene structures are known. For instance, U.S. Pat. No. 6,495,448 describes an additional process for forming a dual damascene structure. However, all such conventional methods include one or more photolithography processing acts which significantly impact the cost of manufacturing semiconductor device structures. Further, elongated conductive elements, such as traces, and discrete conductive structures, such as vias, contacts or bond pads, must be created during separate and distinct processing acts, again increasing the cost and complexity of manufacture.
Accordingly, a method of forming elongated conductive elements and discrete conductive structures in a semiconductor substrate or film that utilizes fewer process acts than conventional processing techniques, uses less material than conventional processing techniques, or may be performed more quickly or more efficiently than conventional processing techniques would be desirable.
U.S. Pat. No. 6,107,109 to Akram discloses a method for fabricating a straight line electrical path from a conductive layer within a semiconductor device to the backside of a semiconductor substrate using a laser beam is disclosed. The method includes forming an opening through a substrate to electrically connect external contacts engaged on a face side thereof to the back side of the substrate. The opening is perpendicular to both the face side and back side of the substrate. In one embodiment, the openings are formed using a laser ablation process.
U.S. Pat. No. 6,114,240 discloses a method for laser ablation to form conductive vias for interconnecting contacts (e.g., solder balls, bond pads and the like) on semiconductor components. In the described method, a laser beam is focused to produce vias having a desired geometry, e.g., hourglass, inwardly tapered, or outwardly tapered.
U.S. Pat. No. 6,696,008 to Brandinger discloses a maskless patterning apparatus which allows for laser beam ablation of one or more layers of material while not etching an underlying different material layer. The apparatus also performs a monitoring function during ablation to determine when to terminate the ablation process.
U.S. patent application Ser. No. 10/673,692 filed Sep. 29, 2003, now U.S. Pat. No. 7,364,985, issued Apr. 29, 2008, and entitled “METHOD FOR CREATING ELECTRICAL PATHWAYS FOR SEMICONDUCTOR DEVICE STRUCTURES USING LASER MACHINING PROCESSES,” assigned to the assignee of the present invention and the disclosure of which is incorporated, in its entirety, by reference herein, discloses a method of laser ablating electrically conductive pathways in a semiconductor substrate or in a film disposed thereon.
Another aspect of conventional semiconductor device fabrication pertains to flip-chip assemblies, wherein a semiconductor die is attached by its active surface to a carrier substrate. Conventionally, a dielectric underfill material, generally an epoxy adhesive, is applied between a surface of an individual semiconductor die and a substrate to which it is (already) electrically attached (i.e., by solder balls, bumps, etc.). The underfill material flows, in liquid form, between the semiconductor die and the carrier substrate, securing and stabilizing the semiconductor die to the carrier substrate.
Conventional dispensing of underfill material may be accomplished via a heated dispensing needle. The dispensing needle is precisely positioned with respect to the semiconductor die and package, because the accuracy of such positioning may greatly affect the resulting performance of the chip. For example, if the dispensing needle is too far from the semiconductor die during dispensing, the space between the semiconductor die and the substrate may not be adequately filled with the underfill material, leading to air voids that can affect performance of the semiconductor die in terms of shorting and environmental degradation. In addition, the dispensing rate and viscosity of the underfill material may be important as affecting uniform filling.
In view of the foregoing, a laser ablation processing technique which may be used for the formation of elongated conductive elements, e.g., traces and the like, in a film, such as a dielectric film on the surface of a semiconductor device or a wafer or other bulk substrate on which a plurality of semiconductor devices are fabricated, would be advantageous. Further, a technique wherein a plurality of different elongated conductive elements and discrete conductive structures may be defined in a single layer (e.g., a film) substantially simultaneously would be desirable. In addition, improved methods for providing an underfill structure for a semiconductor die attached to a carrier substrate would be beneficial.